TSMC announces N4P 5nm node with enhanced performance and efficiency

TSMC continues to make advancements in process node technology. Swiftly following on from the N5 and N4 process nodes is the N4P, bringing further performance and efficiency enhancements to the 5nm node. 

The N4P will offer an 11% performance boost over the N5 and a 6% boost over the N4. Moreover, it will also improve power efficiency by 22% and transistor density by 6% compared to the N5 process technology. Lastly, TSMC’s newly announced node will reduce process complexity and wafer cycle time by reducing the number of masks.

To ensure that customers won’t lose much time migrating their IP, architectures, and other works to N4P, TSMC designed it for easy migration. This will allow customers to maximise their investment as it will be faster to launch products based on the new node to the market.

According to Dr Kevin Zhang, Senior VP of business development at TSMC, the N4P is aimed at HPC and mobile applications, suggesting we might see it being used in future data centre-oriented GPUs and CPUs, as well as on smartphones. The first products based on this new node are expected to tape out by H2 2022.

KitGuru says: What companies might benefit from TSMC’s N4P node for their products? Are you expecting it to see the N4P being as widely used as N7?

The post TSMC announces N4P 5nm node with enhanced performance and efficiency first appeared on KitGuru.

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